Synchronous systems usually use clock signals to operate various components of the circuit. Large complex systems generally have a number of clock signals, each of which drives a set of registers, known as a clock region. Devices route each of these clock signals from the clock source to all the registers that use that clock. The routing of clock signals is often done in such a way that minimizes both the delay and the skew in the delay from the source to the registers. Some devices provide fixed and dedicated clock trees to route clock signals. These clock trees are constructed using fast wires, such that that all routes from the tree root to the leaves are balanced. These wires can often be shielded to provide well-controlled delays. Some trees may span the entire device, while others may span only a subset of the device.
When a circuit is mapped to a device, the registers of a clock region are assigned locations within the device. The clock assigned to a clock region is distributed to registers using a clock tree. Depending on the location of the registers in a clock region, one of a set of fixed clock trees can be selected, the clock source is routed to the root of the tree, and the registers are configured to select the clock tree as the clock input. This process is repeated for all registers in the device.
There can be a large number (e.g., hundreds) of different clock regions in a system. Some clock regions are relatively small in size while other clock regions may span the entire device. Providing the clock signals for all the clock regions can include using a large number of clock trees. When these trees are fixed, then the registers of a clock region may be constrained to fixed locations based on the fixed tree selected for that clock region. As a result, the clock tree selected for the clock region can span the entire area containing registers from that region. In this case, designing a set of appropriately-sized fixed clock trees that are sufficient across the large number of registers and can be programmed into a single device can be challenging. In practice, a significantly large number of fixed clock trees may be required such that all clock regions can be assigned a clock tree.
The excessive use of clock wiring involved in a large number of fixed clock trees can pose computer aided design (CAD) tool challenges as well. For example, it can result in fewer routing resources available for data signals, routing congestion, crosstalk effects on timing analysis, variability noise, and/or the like. Due to the increased complexity with the large number of fixed clock trees, designing placement and clustering of registers to mitigate the negative effects can be difficult with the current CAD system. Therefore, the use and assignment of clock trees to fixed clock regions can constrain placement and clustering of registers, resulting in impaired circuit performance.